EPM240_10 Datasheet, PDF (67/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 5: DC and Switching Characteristics
5–9
Timing Model and Specifications
Figure 5–2. MAX II Device Timing Model
t_R4
Output and Output Enable
Data Delay
Data-In/LUT Chain
User
Flash
Memory
Logic Element
LUT Delay
t_C4
t_LUT
t_COMB
I/O Input Delay
t_IN
Input Routing
Delay
t_DL
Register Control
Delay
t_C
t_CO
t_SU
t_H
t_PRE
t_CLR
t_IODR
t_IOE
Output Routing
Delay
t_FASTIO
I/O Pin
INPUT
t_GLOB
Global Input Delay
To Adjacent LE
Register Delays
From Adjacent LE
Combinational Path Delay
Data-Out
Output
Delay
t_OD
t_XZ
t_ZX
I/O Pin
The timing characteristics of any signal path can be derived from the timing model
and parameters of a particular device. External timing parameters, which represent
pin-to-pin timing delays, can be calculated as the sum of internal parameters.
f Refer to the Understanding Timing in MAX II Devices chapter in the MAX II Device
Handbook for more information.
This section describes and specifies the performance, internal, external, and UFM
timing specifications. All specifications are representative of the worst-case supply
voltage and junction temperature conditions.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during the design compilation if the timing models
are preliminary. Table 5–13 shows the status of the MAX II device timing models.
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing. These
numbers reflect the actual performance of the device under the worst-case voltage
and junction temperature conditions.
Table 5–13. MAX II Device Timing Model Status (Part 1 of 2)
Device
EPM240
EPM240Z (1)
EPM570
EPM570Z (1)
Preliminary
—
—
—
—
Final
v
v
v
v
© August 2009 Altera Corporation
MAX II Device Handbook