EPM240_10 Datasheet, PDF (53/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
4–3
Hot Socketing Feature Implementation in MAX II Devices
1 Make sure that the V_CCINT is within the recommended operating range even though
SRAM download has completed.
Each I/O and clock pin has the circuitry shown in Figure 4–1.
Figure 4–1. Hot Socketing Circuit Block Diagram for MAX II Devices
V_CCIO
Power On
Reset
Monitor
Weak
Pull-Up
Resistor
PAD
Output Enable
Voltage
Tolerance
Control
Hot Socket
Input Buffer
to Logic Array
The POR circuit monitors V_CCINT and V_CCIO voltage levels and keeps I/O pins tri-stated
until the device has completed its flash memory configuration of the SRAM logic. The
weak pull-up resistor (R) from the I/O pin to V_CCIO is enabled during download to
keep the I/O pins from floating. The 3.3-V tolerance control circuit permits the I/O
pins to be driven by 3.3 V before V_CCIO and/or V_CCINT are powered, and it prevents the
I/O pins from driving out when the device is not fully powered or operational. The
hot socket circuit prevents I/O pins from internally powering V_CCIO and V_CCINT when
driven by external signals before the device is powered.
f For information about 5.0-V tolerance, refer to the Using MAX II Devices in Multi-
Voltage Systems chapter in the MAX II Device Handbook.
Figure 4–2 shows a transistor-level cross section of the MAX II device I/O buffers.
This design ensures that the output buffers do not drive when V_CCIO is powered before
V_CCINT or if the I/O pad voltage is higher than V_CCIO. This also applies for sudden
voltage spikes during hot insertion. The V_PAD leakage current charges the 3.3-V
tolerant circuit capacitance.
© October 2008 Altera Corporation
MAX II Device Handbook