EPM240_10 Datasheet, PDF (57/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
4–7
Power-On Reset Circuitry
Figure 4–5. Power-Up Characteristics for MAX II, MAX IIG, and MAX IIZ Devices (Note 1), (2)
V_CCINT
3.3 V
2.5 V
1.7 V
1.4 V
MAX II Device
Approximate Voltage
for SRAM Download Start
Device Resets
the SRAM and
Tri-States I/O Pins
0V
Tri-State
t_CONFIG
User Mode
Operation
Tri-State
V_CCINT
3.3 V
1.8 V
1.55 V
1.4 V
0V
Tri-State
MAX IIG Device
t_CONFIG
User Mode
Operation
Approximate Voltage
for SRAM Download Start
Device Resets
the SRAM and
Tri-States I/O Pins
Tri-State
V_CCINT
3.3 V
1.8 V
MAX IIZ Device
Approximate Voltage
for SRAM Download Start
V_CCINT must be powered down
to 0 V if the V_CCINT
dips below this level
1.55 V
1.4 V
0V
Tri-State
t_CONFIG
minimum 10 µs
User Mode
Operation
Tri-State
t_CONFIG
User Mode
Operation
Notes to Figure 4–5:
(1) Time scale is relative.
(2) Figure 4–5 assumes all V_CCIO banks power up simultaneously with the V_CCINT profile shown. If not, t_CONFIG stretches out until all V_CCIO banks are powered.
1 After SRAM configuration, all registers in the device are cleared and released into
user function before I/O tri-states are released. To release clears after tri-states are
released, use the DEV_CLRn pin option. To hold the tri-states beyond the power-up
configuration time, use the DEV_OE pin option.
© October 2008 Altera Corporation
MAX II Device Handbook