EPM240_10 Datasheet, PDF (74/88 Pages) Altera Corporation – MAX II Device Family Data

5–16
Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
Table 5–21. UFM Block Internal Timing Microparameters (Part 3 of 3)
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed –8 Speed
Grade
Grade
Grade
Grade
Grade
Grade
Symbol
tOE
t_RA
t_{O SC S}
t_{O SC H}
Parameter
Delay from data
register clock to data
register output
Maximum read
access time
Maximum delay
between the
OSC_ENA rising
edge to the
erase/program signal
rising edge
Minimum delay
allowed from the
erase/program signal
going low to
OSC_ENA signal
going low
Min Max Min Max Min Max Min Max Min Max Min Max Unit
180 — 180 — 180 — 180 — 180 — 180 — ns
— 65 — 65 — 65 — 65 — 65 — 65 ns
250 — 250 — 250 — 250 — 250 — 250 — ns
250 — 250 — 250 — 250 — 250 — 250 — ns
Figure 5–3 through Figure 5–5 show the read, program, and erase waveforms for
UFM block timing parameters shown in Table 5–21.
Figure 5–3. UFM Read Waveforms
ARShft
ARClk
ARDin
DRShft
DRClk
DRDin
DRDout
OSC_ENA
Program
Erase
Busy
t_ASU ^tACLK
9 Address Bits t_AH
t_ADH
t_ADS
t_DSS
t_DCO
t_DCLK ^{16 Data Bits t}DSH
MAX II Device Handbook
© August 2009 Altera Corporation