EPM240_10 Datasheet, PDF (79/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 5: DC and Switching Characteristics
5–21
Timing Model and Specifications
Table 5–26 shows the external I/O timing parameters for EPM2210 devices.
Table 5–26. EPM2210 Global Clock External I/O Timing Parameters
MAX II / MAX IIG
–3 Speed Grade –4 Speed Grade –5 Speed Grade
Symbol
Parameter
Condition Min Max Min Max Min Max Unit
tPD1
Worst case pin-to-pin delay 10 pF
—
7.0
—
9.1
— 11.2 ns
through 1 look-up table
(LUT)
t_PD2
Best case pin-to-pin delay
10 pF
—
3.7
—
4.8
—
5.9
ns
through 1 LUT
t_SU
Global clock setup time
—
1.2
—
1.5
—
1.9
—
ns
tH
Global clock hold time
—
0
—
0
—
0
—
ns
tCO
Global clock to output delay 10 pF
2.0
4.6
2.0 6.0
2.0
7.4
ns
tCH
Global clock high time
—
166
—
216
—
266
—
ps
tCL
Global clock low time
—
166
—
216
—
266
—
ps
tCNT
Minimum global clock
period for
16-bit counter
—
3.3
—
4.0
—
5.0
—
ns
f_CNT
Maximum global clock
—
— 304.0 — 247.5 — 201.1 MHz
frequency for 16-bit counter
(1)
Note to Table 5–26:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
External Timing I/O Delay Adders
The I/O delay timing parameters for I/O standard input and output adders, and
input delays are specified by speed grade independent of device density.
Table 5–27 through Table 5–31 show the adder delays associated with I/O pins for all
packages. The delay numbers for –3, –4, and –5 speed grades shown in Table 5–27
through Table 5–33 are based on an EPM1270 device target, while –6, –7, and –8 speed
grade values are based on an EPM570Z device target. If an I/O standard other than
3.3-V LVTTL is selected, add the input delay adder to the external t_SU timing
parameters shown in Table 5–23 through Table 5–26. If an I/O standard other than
3.3-V LVTTL with 16 mA drive strength and fast slew rate is selected, add the output
delay adder to the external t_CO and t_PD shown in Table 5–23 through Table 5–26.
Table 5–27. External Timing Input Delay Adders (Part 1 of 2)
MAX II / MAX IIG
MAX IIZ
–3 Speed –4 Speed –5 Speed –6 Speed –7 Speed –8 Speed
Grade
Grade
Grade
Grade
Grade
Grade
I/O Standard
Min Max Min Max Min Max Min Max Min Max Min Max Unit
3.3-V LVTTL Without Schmitt — 0 — 0 — 0 — 0 — 0 — 0 ps
Trigger
With Schmitt
Trigger
— 334 — 434 — 535 — 387 — 434 — 442 ps
© August 2009 Altera Corporation
MAX II Device Handbook