EPM240_10 Datasheet, PDF (19/88 Pages) Altera Corporation – MAX II Device Family Data

Chapter 2: MAX II Architecture
2–11
Logic Elements
The speed advantage of the carry-select chain is in the parallel precomputation of
carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE
is in the critical path. Only the propagation delays between LAB carry-in generation
(LE 5 and LE 10) are now part of the critical path. This feature allows the MAX II
architecture to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
Figure 2–9 shows the carry-select circuitry in an LAB for a 10-bit full adder. One
portion of the LUT generates the sum of two bits using the input signals and the
appropriate carry-in bit; the sum is routed to the output of the LE. The register can be
bypassed for simple adders or used for accumulator functions. Another portion of the
LUT generates carry-out bits. An LAB-wide carry-in bit selects which chain is used for
the addition of given inputs. The carry-in signal for each chain, carry-in0 or
carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-
higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local,
row, or column interconnects.
Figure 2–9. Carry-Select Chain
LAB Carry-In
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
01
LE0
Sum1
LE1
Sum2
LE2
Sum3
LE3
Sum4
LE4
Sum5
LAB Carry-In
Carry-In0
Carry-In1
data1
data2
LUT
Sum
LUT
LUT
LUT
01
A6
LE5
Sum6
B6
A7
LE6
Sum7
B7
A8
LE7
Sum8
B8
A9
B9
LE8
Sum9
A10
LE9
Sum10
B10
LAB Carry-Out
To top of adjacent LAB
Carry-Out0 Carry-Out1
© October 2008 Altera Corporation
MAX II Device Handbook