AK4695 Datasheet, PDF (99/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
■ MIC Input Recording (4ch)
FS3-0 bits
(Addr:00H, D3-0)
0010
PMMPA/B bit
(Addr:19H, D7-6)
MIC Gain Control
(Addr:04H, 05H)
(1)
>1059/fs
(2)
22H
(3)
MIC Signal Select
(Addr:10H)
00H
(4)
0010
CCH
xxH
Example:
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 48kHz
MIC AMP Gain: +21dB
MIC Power A, B: Output
ALC setting: Refer to Table **
ALCx: Enable
(1) Addr:00H, Data:22H
(2) Addr:19H, Data:C0H
(3) Addr:04H, 05H Data: CCH
(4) Addr:10H, Data: xxH
(5) Addr:09H, 14H, 15H, Data:xxH
ALC Setting
(Addr:09H, 14H, 15H)
xxH
xxH
(5)
(6) Addr:17H, Data:F0H
ALC Enable
(Addr:17H)
00H
(6)
F0H
00H
(11)
(7) Addr:19H, Data:DFH
ALC State
ALC Disable
ALC Enable
ALC Disable
(8) Addr:1AH, Data:1FH
(7)
PMADCx bits
(10)
Recording
(Addr:19H, D4, D3-0)
(9) Addr:1AH, Data:00H
PMDSP bit
(8)
(9)
PMPFILx bits
(Addr:1AH, D4, D3-0)
1059/fs
(10) Addr:19H, Data:C0H
ADC Output
Data
“L” Output
Initialize Normal State “L” Output
(11) Addr:17H, Data:00H
Figure 57. 4ch MIC Input Sequence
(MIC Recording: MICINxL/R  MICx  ADC  ALC  Audio I/F  SDTO1/2)
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. For changing the parameter of ALC, please refer to
“Registers Set-up Sequence in ALC Operation (recording path)”.
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). MIC, ADC and Programmable Filter must be powered-up in
consideration of VCOM rise time after the sampling frequency is changed.
(2) Power up the MIC power supply A and B: PMMPA = PMMPB bits = “0”  “1”
(3) Set up MIC Gain (Addr: 04H, 05H)
(4) Set up MIC input selector (Addr: 10H)
(5) Set up REF value of ALC (Addr: 09H), and ALC Mode (Addr: 14H, 15H)
(6) Enable ALC (Addr: 17H): ALCx bits = “0”  “1”
(7) Power up ADC: PMADx bits = “0”  “1”
MMODE bit must be set to “1”. The initialization cycle time of ADC is 1059/fs=22ms @ fs=48kHz, ADRST
bit = “0”. The ADC outputs “0” data during the initialization cycle.
(8) Power up Programmable Filter: PMDSP = PMPFILx bits = “0”“1”
ALC starts operation from the setting value of IVOL.
(9) Power down Programmable Filter: PMDSP = PMPFILx bits = “1”“0”
(10) Power down ADC: PMADx bits = “1”  “0”
ALC function is disabled. ALCx bits should be set to “0” (Manual Mode) or ADC should be powered down when
changing the sampling frequency and ALC setting. By setting PMADx bits to “0”, the digital volume input gain
setting (IVx7-0 bits) is not reset and the ALC will operate with this setting value when the ADC is powered up
again.
(11) ALC Disable: ALCx bits = “1”  “0”
MS1463-E-01
- 99 -
2014/12