AK4695 Datasheet, PDF (102/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
■ Speaker-Amp Output
FS3-0 bits
(Addr:00H, D3-0)
SPKG1-0 bits
(Addr:03H, D6-)5
DVLB7-0 bits
(Addr:0FH)
DAC Path
(Addr:12H)
DRC Control
(Addr:31H-6EH)
DRC State
PMDRC bit
(Addr:1AH, D7)
PMDACB bit
PMSPLO bit
(Addr:1BH, D2-1)
SPPSN bit
(Addr:02H, D2)
SPP pin
SPN pin
xxxx
(1)
00
84H
32H
00H
(2)
(3)
(4)
(5)
DRC Disable
0010
11
70H
72H
(9)
xxH
DRC Enable
DRC Disable
(10)
(6)
Hi-Z
> 1 ms
(7)
(8)
Normal Output
Hi-Z
Hi-Z
SVDD/2 Normal Output SVDD/2
Hi-Z
Figure 60. Speaker-Amp Output Sequence
Example:
Audio I/F Format: MSB justified
Sampling Frequency:48KHz
Digital Volume B: -10dB
DRC: Enable
Programmable Filter OFF
(1) Addr:00H, Data:22H
(2) Addr:03H, Data:60H
(3) Addr:0FH, Data:70H
(4) Addr:12H, Data:72H
(5) Addr:31H-6EH, Data:xxH
(6) Addr:1AH, Data:80H
Addr:1BH, Data:06H
(7) Addr:02H, Data:04H
Playback
(8) Addr:02H, Data:00H
(9) Addr:12H, Data:32H
(10) Addr:1AH, Data:00H
Addr:1BH, Data:00H
<Example>
At first, clocks must be supplied according to “Clock Set Up” sequence
(1) Set up the sampling frequency (FS3-0 bits). DAC and Speaker-Amp must be powered-up in consideration of
VCOM rise time.
(2) Set up SPK-Amp Gain: SPKG1-0 bits = “00” → “11”
(3) Set up Digital Output Volume B (Addr = 0FH)
(4) Set up the path of SDTI → DRC → DACB → SPK-Amp: DASEL1-0 bits = “00”, DACS bit = “0” → “1”,
DRCENB bit = “1”
(5) Set up DRC Control (Addr = 31H ~ 6EH)
(6) Power up DACB, DRC and SPK-Amp: PMDACB = PMDRC = PMSPLO bits = “0” → “1”
(7) Exit SPK-Amp power save mode: SPPSN bit = “0” → “1”
(8) Enter SPK-Amp power save mode: SPPSN bit = “1” → “0”
(9) Set up the path of SDTI → DRC → DACB → SPK-Amp: DACS bit = “1” → “0”
(10) Power down DAC, DRC and SPK-Amp: PMDACB = PMDRC = PMSPLO bits = “1” → “0”
MS1463-E-01
- 102 -
2014/12