AK4695 Datasheet, PDF (68/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
DACA
LOUTA pin
ROUTA pin
1k
1F
22k
Figure 44. External Circuit of Stereo Line Output A (in case of using a Pop Noise Reduction Circuit)
[Stereo Line Output A Control Sequence (in case of using a Pop Noise Reduction Circuit)]
(2)
PMLO bit
(1)
(3)
LOPSA bit
(5)
(4)
(6)
LOUTA, ROUTA pins
Normal Output
99% Common Voltage
1% Common Voltage
max.?300 ms
max. 300 ms
Figure 45. Stereo Line Output A Control Sequence (in case of using a Pop Noise Reduction Circuit)
(1) Set LOPSA bit = “1”. Stereo line output enters standby mode.
(2) Set PMLO bit = “1”. Stereo line output exits power-down mode.
LOUTA and ROUTA pins rise up to common voltage. Rise time is 200ms (max 300ms) when C=1F.
(3) Set LOPSA bit = “0” after LOUTA and ROUTA pins rise up. Stereo line output exits standby mode.
Stereo line output is enabled.
(4) Set LOPSA bit = “1”. Stereo line output enters standby mode.
(5) Set PMLO bit = “0”. Stereo line output enters power-down mode.
LOUTA and ROUTA pins fall down to 1% of the common voltage. Fall time is 200ms (max 300ms) at C=1F.
(6) Set LOPSA bit = “0” after LOUTA and ROUTA pins fall down. Stereo line output exits standby mode.
2. LMODE bit = “0” (using a same connector for both Line input and output)
When PMLO bit is “0”, LOUTA and ROUTA pins are in power-down mode and output Hi-Z signal.
When PMLO bit is “1”, the LOUTA/ROUTA pin enters power-save mode and the output is pulled-down to common
voltage via an internal resistor of 200k(typ). In this case, the signal path of the stereo line output (DACA) is OFF. Pop
noise can be reduced by using power save mode by LMODE bit = “1”. Line input should be made in power-save mode.
PMLO bit LOPSA bit
Mode
LOUTA/ROUTA pin
0
x
Power Down
Hi-Z
(default)
1
x
Power Save
Common Voltage
by 200k
Table 74. Stereo Line Output Mode Setting @ LMODE bit = “0” (x: Don’t care)
MS1463-E-01
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2014/12