AK4695 Datasheet, PDF (67/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
PMVCM bit
0
1
PMBP bit
0
1
0
1
Mode
Input Resistance
(BEEPIN pin)
Power Down
Hi-Z
Power Save
Common Voltage
by 50kΩ
Normal Operation
Common Voltage
by 50kΩ
Table 71. BEEP Input Mode Setting
(default)
■ Stereo Line Output A (LOUTA, ROUTA pin)
When PMLO bit is set to “1”, L and R channel signals of DAC are output in single-ended format via LOUTA and ROUTA
pins. The DAC output can be OFF by setting PMDACA bit to “0”. In this case, LOUTA and ROUTA pins output common
voltage. The load impedance is minimum 10k. The stereo line output gain is controlled by LVOL bit. There are two
power save modes for stereo line outputs so that common connectors can be used for stereo output and line input.
DACA
“LVOL bit”
LOUTA pin
ROUTA pin
Figure 43. Stereo Line Output A
LVOL bit
Gain
0
-0.4dB (default)
1
+3.2dB
Table 72. Stereo Line Output A Gain
1. LMODE bit = “1” (default) (Line output and input are independent)
When PMLO bit LOPSA bits are “0”, output signals are muted and LOUT and ROUT pins output common voltage. When
PMLO bit = LOPSA bit = “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS by
100k(typ). When LOPSA bit is “1”, stereo line output enters standby mode. Pop noise at power-up/down can be reduced
by changing PMLO bit when LOPSA bit = “1”. In this case, output signal line should be pulled-down by 22k after AC
coupled as Figure 44. Rise/Fall time is maximum 300ms (@AVDD=2.8V) when C=1F. When PMLO bit = “1” and
LOPSA bit = “0”, stereo line output is in normal operation.
LOPSA bit PMLO bit
Mode
LOUTA/ROUTA pin
0
0
Power down
Pull-down to VSS
by 100kΩ
1
Normal Operation
Normal Operation
1
0
1
Standby
Standby
Fall down to VSS
Rise up to common voltage
Table 73. Mode Setting of Stereo Line Output A @ LMODE bit = “1”
(default)
MS1463-E-01
- 67 -
2014/12