AK4695 Datasheet, PDF (63/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
2. DRC Recovery Operation
During the DRC recovery operation, when the DRC volume reaches 0dB or the output level of DRC exceeds limiter
detection level, the DRC volume are set automatically by soft transition in the recovery speed set by DRGAIN1-0 bits
(Table 65).
DRGAIN1
bit
0
0
1
1
DRGAIN0
bit
Recovery Speed
8kHz
16kHz
48kHz
0
1.1dB/s
2.1dB/s
6.4dB/s
1
2.1dB/s
4.2dB/s 12.7dB/s
0
4.2dB/s
8.5dB/s 25.4dB/s
1
8.5dB/s
17.0dB/s 50.9dB/s
Table 65. DRC Recovery Speed Setting
(default)
MS1463-E-01
- 63 -
2014/12