AK4695 Datasheet, PDF (43/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
4. Example of registers set-up sequence of ALC Operation
The following registers must not be changed during ALC operation. These bits must be changed after ALC operation is
finished by ALC3-0 bits = “0”. The reference level can be changed during ALC operation. If the reference level is reduced
the volume level is changed by soft transition in 0.02548dB/fs step. The volume is also changed by soft transition to the
IVOL setting value (IVx7-0 bits) until manual mode starts after ALCx bit is set to “0”. Do not change the REF value during
soft transition when REF7-0 bits are set to 00H (MUTE).
When changing ALC operation channels, finish all ALC operations at first (ALC3-0 bits = “0”) and write ALCx bit = “1”.
In this case, ALCx bit writing must be made with an interval of 2/fs. It is recommended that ALC operation is enabled after
transition time since the volume changes to the IVOL setting value by soft transition when ALC operation is finished.
The reference volume and IVOL should be set to a value more than 0dB or mute when ATTLMT bit = “1”. Do not set
ATTLMT bit to “1” during the soft transition of when changing the REF value from 0dB or more to MUTE and vice versa.
LMTH1-0, WTM1-0, RFST1-0, ATTLMT and ALCEQN bits
Manual Mode
Example:
Recovery Wait Time = 21.3ms@48kHz
Recovery Quantity = 0.00106dB (2/fs)
Fast Recovery Quantity = 0.0032 dB
Maximum Gain = +30.0dB
Limiter Detection Level = 4.1dBFS
ALCx bit = “1”
WR (REF7-0)
WR (IVx7-0)
* The value of IVx should be
the same or smaller than REF’s
(1) Addr=09H, Data=B0H
(2) Addr=0AH-0DH, Data=B0H
WR (LMTH1-0, WTM 1-0, RGAIN2-0
RFST1-0, ATTLMT, ALCEQN)
(3) Addr=14H, Data=3DH
Addr=15H, Data=00H
WR (ALCx = “1”)
(4) Addr=17H, Data=F0H
ALC Operation
Figure 31. Registers Set-up Sequence in ALC Operation (recording path)
MS1463-E-01
- 43 -
2014/12