AK4695 Datasheet, PDF (22/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
■ System Reset
Upon power-up, the AK4695 must be reset by bringing the PDN pin = “L”. This reset is released when a dummy command
is input (sequential write is not available) after the PDN pin = “H”. This ensures that all internal registers reset to their
initial value. Dummy command is executed by writing all “0” to the register address 00H. It is recommended to set the
PDN pin = “L” before power up the AK4695.
CSN
CCLK _{“H” or “L”}
0 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
“H” or “L”
CDTIO “H” or “L”
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
R/W: READ/WRITE (“1”: WRITE)
A6-A0: Register Address (00H)
D7-D0: Control data (Input), (00H)
Figure 13. Dummy Command in 3-wire Serial Mode
The ADC enters an initialization cycle when the PMAD0, PMAD1, PMAD2 or PMAD3 bit is changed from “0” to “1”.
PMMPA and PMMPB bits must be set to “1” before writing PMAD0, PMAD1, PMAD2 or PMAD3 bit “1” even when not
using the microphone power. Set PMMPA and PMMPB bits to “0” after the initialization cycle if the microphone power is
not necessary. The initialization cycle time is set by ADRST bit (Table 4). During the initialization cycle, the ADC digital
data outputs of both channels are forced to a 2's complement, “0”. The ADC output reflects the analog input signal after the
initialization cycle is complete. When using a digital microphone, the initialization cycle is the same as ADC’s.
Note 43. The initial data of ADC has offset data that depends on the condition of the microphone and the cut-off frequency
of HPF. If this offset is not small, make initialization cycle longer by setting ADRST bit or do not use the initial
data of ADC.
ADRST bit
0
1
Cycle
1059/fs
267/fs
Init Cycle
fs = 8kHz
fs = 16kHz
132.4ms
66.2ms
33.4ms
16.7ms
Table 4. ADC Initialization Cycle
fs = 48kHz
22.1ms
5.6ms
(default)
MS1463-E-01
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2014/12