AK4695 Datasheet, PDF (38/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block when ALC bit is “1”. When PFSEL bit is “0”, ALC circuit
operates at recording path. When PFSEL bit is “1”, ALC circuit operates at playback path. The calculating delay time does
not differ on each channel whether ALC is ON or OFF. ALC block is powered up when PMDSP bit= PMPFILx bits=
ALCx bits = “1”. Each channel can be powered down individually by PMPFIL3-0 bits. The powered-down channel by
PMPFFIL3-0 bits outputs “0” data.
The ALC block consists of these blocks shown below. ALC limiter detection level and ALC recovery wait counter reset
level are monitored at Level Detection 2 block after EQ block. The Level Detection 1 block also monitors clipping
detection level (+0.53dBFS).
Input
ALC
Control
Level
Detection 2
EQ
Level
Detection 1
Volume
Figure 29. ALC Block
Output
The polar (fc₁) and zero-point (fc₂) frequencies of EQ block are dependent on the sampling frequency. The coefficient is
changed automatically according to the sampling frequency range setting. When ALC EQ block is OFF (ALCEQ bit = “1”),
these level detection are off.
Sampling Frequency Range
8kHz  fs  16kHz
(FS3-2 bits = “11”)
8kHz  fs  32kHz
(FS3-2 bits = “01”)
8kHz  fs  48kHz
(FS3-2 bits = “00”)
32kHz < fs  48kHz
(FS3-2 bits = “10”)
Polar Frequency (fc1)
150Hz
Zero-point Frequency (fc2)
100Hz
fs=12kHz
150Hz
100Hz
fs=24kHz
150Hz
100Hz
Table 21. ALCEQ Frequency Setting
fs=48kHz
fs: Sampling Frequency
fc₁: Polar Frequency
fc₂: Zero-point Frequency
1 + 1 / tan (fc₂/fs)
A = 10^K/20 x
,
1 + 1 / tan (fc₁/fs)
1  1 / tan (fc₁/fs)
1  1 / tan (fc₂/fs)
B=
, C = 10^K/20 x
1 + 1 / tan (fc₁/fs)
1 + 1 / tan (fc₁/fs)
Transfer function
A + Cz ^1
H(z) =
1 + Bz ^1
MS1463-E-01
- 38 -
2014/12