AK4695 Datasheet, PDF (75/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
■ Serial Control Interface
1. Data Writing and Reading Modes on Every Address
Single data is written to (read from) one address. Internal registers may be written by using 3-wire serial interface pins
(CSN, CCLK and CDTIO). The data on this interface consists of Read/Write, Register address (MSB first, 7bits) and
Control data or Output data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. Data writings become available on the rising edge of CSN. When reading the data, the
CDTIO pin changes to output mode at the falling edge of 8th CCLK and outputs data in D7-D0. However this reading
function is available only when READ bit = “1”. When READ bit = “0”, the CDTIO pin stays as Hi-Z even after the falling
edge of 8th CCLK. The data output finishes on the rising edge of CSN. The CDTIO pin is placed in a Hi-Z state except
when outputting the data at read operation mode. Clock speed of CCLK is 5MHz (max.). The values of internal registers
are initialized by the PDN pin = “L”.
CSN
CCLK _{“H” or “L”}
0 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
“H” or “L”
CDTIO “H” or “L”
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
R/W:
A6-A0:
D7-D0:
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 53. Serial Control Interface Timing
2. Continuous Data Writing Mode
Address is incremented automatically and data is written continuously. This mode does not support reading. When the
written address reaches 6EH, it is automatically incremented to 00H.
In this mode, registers are written by 3-wire serial interface pins (CSN, CCLK and CDTIO). The data on the 3-wire serial
interface is 8 bit data, consisting of register address (MSB-first, 7bits) and control or output data (MSB-first, 8xN bits)).
The receiving data is latched on a rising edge (“”) of CCLK. The first write data becomes effective between the rising
edge (“”) and the falling edge (“”) of 16th CCLK. When the micro processor continues sending CDTI and CCLK clocks
while the CSN pin = “L”, the address counter is incremented automatically and writing data becomes effective between the
rising edge (“”) and the falling edge (“”) of every 8th CCLK. For the last address, writing data becomes effective
between the rising edge (“”) of 8th CCLK and the rising edge (“”) of CSN. The clock speed of CCLK is 5MHz (max).
The internal registers are initialized by the PDN pin = “L”.
Even through the writing data does not reach the last address; a write command can be completed when the CSN pin is set
to “H”.
Note 52. When CSN “” was written before “” of 8th CCLK in continuous data writing mode, the previous data writing
address becomes valid and the writing address is ignored.
Note 53. After 8bits data in the last address became valid, put the CSN pin “H” to complete the write command. If the
CDTI and CCLK inputs are continued when the CSN pin = “L”, the data in the next address, which is incremented,
is over written.
MS1463-E-01
- 75 -
2014/12