AK4695 Datasheet, PDF (73/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
■ Stereo Line Output B (LOUTB/ROUTB pin: LBSEL bit = “1”)
When LBSEL bit = “1” and DACS1-0 bits = “01”, L and R channel signals of DACB are output in single-ended format via
LOUTB and ROUTB pins. When DACS bit is “0”, output signals are muted and LOUTB and ROUTB pins output
common voltage. The load impedance is 10k (min.). When the PMSPLO bit = “0” and LOPSB bit = “0”, the stereo line
output B enters power-down mode and outputs Hi-Z. The stereo line output B is powered up when PMSPLO bit = “1” and
LOPSB bit = “0”. By setting LOPSB bit to “1” while PMSPLO bit = “1”, LOUTB and ROUTB pins enter power-save
mode and output common voltage via internal resistance of 200k (typ.). In this case, the signal path to the stereo line
output (DACB) is OFF. When PMSLO bit is “1”, writing “0” to LBSEL bit is ignored.
Depending on the power supply conditions, the stereo line output B is clipped when a 0dBFS signal is input from DACB.
The following condition should be observed to avoid this clipping. SVDD ≥ AVDD
DACB Lch
DACS bit
LOUTB pin
DACB Rch
ROUTB pin
BEEPIN pin
Beep-amp
BEEPS bit
Figure 50. Stereo Line Output B
LOPSB bit
0
1
PMSPLO bit
Mode
LOUTB/ROUTB pin
0
Power-down
Hi-Z
1
Normal Operation Normal Operation
0
N/A
1
Power-save
Common Voltage
by 200k
Table 79. Stereo Line Output B Mode Select (N/A: Not Available)
(default)
MS1463-E-01
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2014/12