AK4695 Datasheet, PDF (72/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
■ Speaker Output (SPP/SPN pins: LBSEL bit = “0”)
The DACB output signal is input to the speaker amplifier as [(L+R)/2] when LBSEL bit = “0” and DACS bit = “1”. The
speaker amplifier is mono and BTL output. The gain is set by SPKG1-0 bits and the output level depends on this setting. In
the condition that AVDD > SVDD, the speaker amplifier output is clipped by a 0dBFS input from DACB. The DACB
output level should be set to a lower level by setting DVLB bits to avoid this clipping.
SPKG1-0 bits
00
01
10
11
SPK-Amp Gain (BTL)
5.6dB
7.6dB
9.6dB
14.6dB
Table 76. SPK-Amp Gain
(default)
SPKG1-0 bits
SPK-Amp Output (Note 51)
(DAC Input =0dBFS, AVDD=SVDD=2.8V)
00
3.91Vpp
01
4.92Vpp
10
6.20Vpp
11
11.02Vpp
Note 51. The output level is calculated by assuming that output signal is not clipped. In the actual case, the output signal
may be clipped when DACB outputs a 0dBFS signal. The DACB output level should be set to a lower level by
setting digital volume (DVLB bits) so that the speaker amplifier output is not clipped.
Table 77. SPK-Amp Output Level
< Speaker-Amp Control Sequence >
The speaker amplifier is powered-up/down by PMSPLO bit. When PMSPLO bit is “0”, both SPP and SPN pins are in a
Hi-Z state. When PMSPK bit is “1” and SPPSN bit is “0”, the speaker amplifier enters power-save mode. In this mode, the
SPP pin is placed in a Hi-Z state and the SPN pin outputs SVDD/2 voltage.
When the PMSPLO bit is “1”, writing “1” to LBSEL bit is ignored. The SPP and SPN pins rise up in power-save mode
setting PMSPLO bit to “0” after the PDN pin is changed from “L” to “H”. In this mode, the SPP pin is placed in a Hi-Z state
and the SPN pin goes to SVDD/2 voltage. Because the SPP and SPN pins rise up in power-save mode, pop noises are
reduced. When the AK4695 is powered-down, a pop noise can also be reduced by first entering power-save mode.
PMSPLO bit
0
1
SPPSN bit
Mode
SPP pin
SPN pin
x
Power-down
Hi-Z
Hi-Z
0
Power-save
Hi-Z
SVDD/2
1
Normal Operation Normal Operation Normal Operation
Table 78 Speaker-Amp Mode Setting (x: Don’t care)
(default)
PMSPLO bit
SPPSN bit
>1ms
SPP pin
Hi-Z
Hi-Z
SPN pin Hi-Z ^SVDD/2
SVDD/2
Hi-Z
Figure 49. Power-up/Power-down Timing for Speaker-Amp
MS1463-E-01
- 72 -
2014/12