AK4695 Datasheet, PDF (62/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
3. Dynamic Range Control Block
The AK4695 has the dynamic range control (DRC) circuits. The compression level is selected in three levels and set by
DRCC1-0 bits (Table 63).
When the DRC is OFF (DRCC1-0 bits = “00”), the audio data passes this block by 0dB gain. However limiter and recovery
operation is always ON. The compression level must be set when PMDRC bit = “0”.
Low Mid
DRC Off
0dB
High
-6dB
-6dB
DRC Input Level (dB)
Figure 40. DRC Gain Curve
0dB +1.9dB
+1.0dB +3.5dB
DRCC1 bit DRCC0 bit Compression Level
0
0
OFF
0
1
Low
1
0
Middle
1
1
High
Table 63. DRC Compression Level Select
(default)
1. DRC Limiter Operation
During the DRC limiter operation, when the output level of DRC exceeds full-scale, the DRC volume are attenuated
automatically with the soft transition in the attenuation speed set by DLMAT2-0 bits (Table 64).
DLMAT2
bit
0
0
0
0
1
1
1
1
DLMAT1 DLMAT0
bit
bit
8kHz
ATT Speed
16kHz
48kHz
0
0
0.1dB/ms 0.3dB/ms 0.8dB/ms
0
1
0.3dB/ms 0.5dB/ms 1.6dB/ms
1
0
0.5dB/ms 1.1dB/ms 3.3dB/ms
1
1
1.1dB/ms 2.2dB/ms 6.6dB/ms
0
0
2.2dB/ms 4.4dB/ms 13.2dB/ms
0
1
4.5dB/ms 9.0dB/ms 26.9dB/ms
1
0
1
1
N/A
Table 64. DRC ATT Speed Setting (N/A: Not Available)
(default)
MS1463-E-01
- 62 -
2014/12