AK4695 Datasheet, PDF (70/107 Pages) Asahi Kasei Microsystems – 24bit 4ch CODEC with MIC/HP/SPK/LINE-AMP

[AK4695]
■ Charge Pump Circuit
The internal charge pump circuit generates negative voltage (PVEE) from SVDD voltage. The PVEE voltage is used for
the headphone amplifier. The charge pump circuit starts operation when PMHPL or PMHPR bit = “1” and PMDACB bit =
“1”. PMVCM bit must be set “1” to power up the charge pump circuit. The power-up time of the charge pump circuit is
8ms (max). The headphone amplifier will be powered up after the charge pump circuit is powered up (when PMHPL or
PMHPR bit = “1”). The operating frequency of the charge pump circuit is dependent on the sampling frequency.
■ Headphone Amplifier (HPL/HPR pins)
The positive voltage of the headphone amplifier uses the power supply to the DVDD pin, therefore 200mA of the
maximum power supply capacity is needed. The internal charge pump circuit generates negative voltage (PVEE) from
SVDD voltage. The headphone amplifier output is single-ended and centered around on VSS (0V). Therefore, the
capacitor for AC-coupling can be removed. The minimum load resistance is 16. The headphone amplifier output may be
clipped when a 0dB signal is input from DACB depending on the power supply conditions. The headphone amplifier
should be used in the following condition to avoid this clipping.
SVDD ≥ AVDD, DVDD ≥ 0.54 x AVDD
<External Circuit of Headphone-Amp>
An oscillation prevention circuit (0.22μF±20% capacitor and 100Ω±20% resistor) should be put because it has the
possibility that Headphone-Amp oscillates in type of headphone.
DACB
HP-AMP
HPL pin
HPR pin
Headphone
AK4695
0.22μ
16Ω
100Ω
Figure 48. External Circuit of Headphone-Amp
When PMDACB bit = “1”, HPZ bit = “0”, DACAST bit = “1” and PMHPL, PMHPR bits = “1”, headphone outputs are in
normal operation. The headphone-amps are powered-down completely by setting PMHPL and PMHPR bits = “0”. At that
time, the HPL and HPR pins go to VSS voltage via the internal pulled-down resistor. The pulled-down resistor is 10 (typ).
The HPL and HPR pins become Hi-Z state by setting HPZ bit to “1” when PMHPL and PMHPR bit = “0”. The power-up
time of the headphone-amps is 26ms (max.), and power-down is executed immediately.
PMVCM
bit
x
x
1
1
PMHP bit HPZ bit
Mode
HPL/R pins
0
0
Power-down & Mute
Pull-down by 10 (typ)
0
1
Power-down
Hi-Z
1
0
Normal Operation
Normal Operation
1
1
N/A
N/A
Table 75. Headphone Output Status (x: Don’t’ care, N/A: Not available)
(default)
MS1463-E-01
- 70 -
2014/12