AK8858 Datasheet, PDF (9/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[AK8858]
Pin
No.
Symbol
P/S I/O Functional Description
27 DVSS
28 DTCLK
DG
P1 O
Digital ground pin.
Data clock output pin.^(*1)
29 PVDD1
30 DATA7
31 DATA6
32 DATA5
P1 P
P1 O
P1 O
P1 O
I/O power supply pin.
DATA output pin.^(*1)
DATA output pin.^(*1)
DATA output pin.^(*1)
33 DVSS
D G Digital ground pin.
34 PVDD1
35 DATA4
36 DATA3
37 DATA2
38 DATA1
P1 P
P1 O
P1 O
P1 O
P1 O
I/O power supply pin.
DATA output pin.^(*1)
DATA output pin.^(*1)
DATA output pin.^(*1)
DATA output pin.^(*1)
39 DVDD
D P Digital power supply pin.
40 DVSS
D G Digital ground pin.
41 PVDD1
42 DATA0
P1 P
P1 O
I/O power supply pin.
DATA output pin.^(*1)
DVALID/ FIELD signal output pin.
43
DVAL_FLD P1
O DVALID signal output / FIELD signal output can be selected by register
(I/O) setting.^(*1)
If test mode, it is I/O pin.
44 VD_FLD
45 HD
P1
O
(I/O)
VD/ FIELD signal output pin
VD signal output / FIELD signal output can be selected by register setting.^(*1)
If test mode, it is I/O pin.
P1
O HD signal output pin.^(*1)
(I/O) If test mode, it is I/O pin.
46 DVSS
D G Digital ground pin.
47 TEST0
P2 I
Pin for test mode setting. Connect to DVSS.
48 TEST1
P2 I
Pin for test mode setting. Connect to DVSS.
Shows status of synchronization with input signal
49 NSIG
P2 O
Low: Signal present (synchronized).
High: Signal not present or not synchronized.^(*1)
Output Enable pin.
50 OE
P2 I
Low: Digital output pin in Hi-z output mode.
High: Data output mode.
Hi-z input to OE pin is prohibited.
51 PVDD2
P2 P Microprocessor I/F power supply pin.
Reset signal input pin. Hi-z input is prohibited.
52 RSTN
P2 I
Low: Reset.
High: Normal operation.
Power-down control pin. Hi-z input is prohibited.
53 PDN
P2 I
Low: Power-down.
High: Normal operation.
54 SDA
P2 I/O
I2C data pin. Connect to PVDD2 via a pull-up register.
Hi-z input possible when PDN=L.
55 SCL
P2 I
I2C clock input pin. Connect to PVDD2 via a pull-up register.
Hi-z input possible when PDN=L.
I2C bus address selector pin.
56 SELA
P2 I
PVDD2 connection: Slave address [0x8A]
DVSS connection: Slave address [0x88]
57 AVDD
A P Analog power supply pin.
[Power supply] A: AVDD, D: DVDD, P1: PVDD1, P2: PVDD2
[Input/Output] I: intput pin, O: output pin, I/O: input/output pin, P: power supply pin, G: ground connection pin
(*1)_{See {[3.2] Output pin state} for relation of output to OE/PDN and RSTN pin status.}
MS1230-E-00
-9-
2010/9