AK8858 Datasheet, PDF (67/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[9.1.3] Clamp Control 2 Register (R/W) [Sub Address 0x02]
Clamp pulse control setting.
[AK8858]
Sub Address: 0x02
bit 7
bit 6
Reserved
Reserved
Default Value
0
0
bit 5
Reserved
0
bit 4
YPBPRCP
0
bit 3
UDG1
0
bit 2
UDG0
0
Default Value: 0x01
bit 1
bit 0
CLPG1 CLPG0
0
1
Clamp Control 2 Register
BIT Register Name
bit 0 CLPG0
~
~
bit 1 CLPG1
Clamp Gain
bit 2 UDG0
~
~
bit 3 UDG1
bit 4 YPBPRCP
bit 5
~
Reserved
bit 7
Up Down Gain
YPbPr Clamp
Reserved
R/W Definition
Current value of fine clamp in analog circuit setting
CLPG[1:0]
R/W
00: Min
01: Middle 1 (default)
10: Middle 2
11: Max
Current value of rough clamp in analog circuit setting
[ UDG1 : UDG0 ]
R/W
00: Min (default)
01: Middle 1
10: Middle 2
11: Max
Clamp position of PbPr signal input setting
R/W 0: YPbPr sync tip timing
1: Y sync tip timing / PbPr backporch
R/W Reserved
MS1230-E-00
- 67 -
2010/9