AK8858 Datasheet, PDF (76/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[9.1.12] Control 0 Register (R/W) [Sub Address 0x0B]
[AK8858]
Sub Address: 0x0B
bit 7
bit 6
DVAL_FP
VD_FP
Default Value
0
0
bit 5
HDP
0
bit 4
C443FIL1
0
bit 3
C443FIL0
0
bit 2
C358FIL1
0
Default Value: 0x00
bit 1
bit 0
C358FIL0
AGCTL
0
0
Control 0 Register
BIT Register Name
bit 0 AGCTL
AGC Transition Level
bit 1 C358FIL0
~
~
bit 2 C358FIL1
C Filter 358 Select
bit 3 C443FIL0
~
~
bit 4 C443FIL1
bit 5 HDP
C Filter 443 Select
HD pin Polarity
bit 6 VD_FP
VD_F Pin Polarity
bit 7 DVAL_FP
DVAL_FLD pin Polarity
R/W Definition
Transition speed setting,
R/W
between peak AGC and sync AGC
0: QUICK
1: SLOW
C-filter bandwidth setting,
for 3.58 MHz subcarrier system signal
C358FIL[1:0]
R/W 00: Narrow
01: Middle
10: Wide
11: Reserved
C-filter bandwidth setting,
for 4.43 MHz subcarrier system signal
C443FIL[1:0]
R/W 00: Narrow
01: Middle
10: Wide
11: Reserved
HD signal polarity setting
R/W 0: ACTIVE LOW
1: ACTIV HIGH
VD_FLD pin output signal polarity setting
If VD signal is output
R/W
0: ACTIVE LOW
1: ACTVIE HIGH
If FIELD signal is output
0: LOW=ODD / HIGH=EVEN
1: LOW=EVEN / HIGH=ODD
DVAL_FLD pin output signal polarity setting
If DVALID signal is output
R/W
0: ACTIVE LOW
1: ACTVIE HIGH
If FIELD signal is output
0: LOW=ODD / HIGH=EVEN
1: LOW=EVEN / HIGH=ODD
MS1230-E-00
- 76 -
2010/9