AK8858 Datasheet, PDF (68/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[9.1.4] Miscellaneous Setting Register (R/W) [Sub Address 0x03]
[AK8858]
Sub Address: 0x03
bit 7
bit 6
VERTS CSCAN
Default Value
0
0
bit 5
Reserved
0
bit 4
CMPSEL
0
bit 3
CSCL
0
bit 2
CSSL
0
Default Value: 0x00
bit 1
bit 0
Reserved
Reserved
0
0
Miscellaneous Setting Register
BIT Register Name
bit 0
~
Reserved
bit 1
Reserved
bit 2 CSSL
bit 3 CSCL
Component
Signal
Sync Level
Component
Signal
Color Level
bit 4 CMPSEL
Component
Signal Select
bit 5 Reserved
bit 6 CSCAN
Reserved
Color stripe
cancel
bit 7 VERTS
* Set CSCAN to [1].
Vertical
SYNC way
R/W Definition
R/W Reserved
YPbPr signal sync / luminance ratio level setting
R/W 0: 300/700
1: 286/714
Color (PbPr) signal level setting
R/W 0: 700mV
1: 714mV
Component signal input, interlace / progressive setting
R/W
(auto detection mode is disable).
0: Interlace (525i/625i)
1: Progressive (525p/625p)
R/W Reserved
Color stripe cancel operation*
R/W 0: not operated
1: operated
Vertical sync mechanism setting
R/W 0: VLOCK mechanism
1: Direct lock mechanism
MS1230-E-00
- 68 -
2010/9