AK8858 Datasheet, PDF (51/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[7.26.2.5] Pin polarity
Register
Name
HDP
VD_FP
DVAL_FP
Pin name
HD
VD_FLD
DVAL_FLD
Signal
HD
VD
Field
DVALID
Field
Setting
[0]
Active Low
Active Low
Low: Odd-Field
High: Even-Field
Active Low
Low: Odd-Field
High: Even-Field
DTCLK polarity
Name
CLKINV
Definition
[0]: Normal output ( rise edge to data)
[1]: Inverted( fall edge to data)
[7.26.2.6] Timing signal on fixed clock mode
[AK8858]
Sub Address: 0x0B [7:5]
[1]
Active High
Active High
Low: Even-Field
High: Odd-Field
Active High
Low: Even-Field
High: Odd-Field
Sub Address: 0x07 [7]
DTCLK
HD
DVALID
DATA [7:0]
FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1
FF 00 00 EAV
FF
HD
ACTSTRT
Fixed
ACT
ACTEND
Not fixed
MS1230-E-00
- 51 -
2010/9