AK8858 Datasheet, PDF (73/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[9.1.9] Output Data Start and Delay Control Register (R/W) [Sub Address 0x08]
Ouput data timing setting register.
[AK8858]
Sub Address: 0x08
bit 7
bit 6
Reserved ACTSTAT2
Default Value
0
0
bit 5
ACTSTAT1
0
bit 4
ACTSTAT0
0
bit 3
Reserved
0
bit 2
YCDELAY2
0
Default Value: 0x00
bit 1
bit 0
YCDELAY1 YCDELAY0
0
0
Output Data Start and Delay Control Register
BIT Register Name
R/W
Definition
Adjustment of Y and C timing.
In D1 decode, delay or advance 1 sample unit is about 74ns
In D2 decode, delay or advance 1 sample unit is about 37ns.
bit 0 YCDEALY0
~~
bit 2 YCDELAY2
bit 3 Reserved
YC Delay
Control
Reserved
YCDELAY[2:0]
[001]: Y advance 1-sample toward C.
R/W [010]: Y advance 2-sample toward C.
[011]: Y advance 3-sample toward C.
[000]: No Delay and advance.
[101]: Y delay 3-sample toward C.
[110]: Y delay 2-sample toward C.
[111]: Y delay 1-sample toward C.
[100]: Reserved
R/W Reserved
Fine-tuning video data decode start position
In D1 decode, delay or advance 1 sample unit is about 74ns
In D2 decode, delay or advance 1 sample unit is about 37ns.
bit 4 ACTSTA0
~~
bit 6 ACTSTA2
bit 7 Reserved
Active Video
Start Control
Reserved
ACTSTA[2:0]
[001]: 1-sample delay
R/W [010]: 2-sample delay
[011]: 3-sample delay
[000]: Normal start position
[101]: 3-sample advance
[110]: 2-sample advance
[111]: 1-sample advance
[100]: Reserved
R/W Reserved
MS1230-E-00
- 73 -
2010/9