AK8858 Datasheet, PDF (72/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[9.1.8] Output Control Register (R/W) [Sub Address 0x07]
Output pin status register setting.
[AK8858]
Sub Address: 0x07
bit 7
bit 6
CLKINV
DVALFSEL
Default Value
0
0
bit 5
VDFSEL
0
bit 4 bit 3 bit 2
HL
NL
DVALFL
0
0
0
Default Value: 0x00
bit 1
bit 0
VDFL
DL
0
0
Output Control Register
BIT Register Name
R/W Definition
bit 0 DL
Data Output Low bit
R/W
0: Normal output
1: [D17: D0] pin output fixed at Low
bit 1 VDFL
VD_FLD
Output Low bit
R/W
0: Normal output
1: VD_FLD pin output fixed at Low
bit 2 DVALFL
DVAL_FLD
Output Low bit
R/W
0: Normal output
1: DVAL_FLD pin output fixed at Low
bit 3 NL
NSIG Output Low bit
R/W
0: Normal output
1: NSIG pin output fixed at Low
bit 4 HL
HD Output Low bit
R/W
0: Normal output
1: HD pin output fixed at Low
bit 5 VDFSEL
VD_FLD Select bit
R/W
0: VD signal output
1: FIELD signal output
bit 6 DVALFSEL
DVAL_FLD Select bit
R/W
0: DVALID signal output
1: FIELD signal output
bit 7 CLKINV
Clock Invert Setting
R/W
0: Normal output (write in data at rising edge)
1: Data and clock reversed (write in data at falling edge)
Note: Output control via pins OE, PDN, and RSTN takes priority, regardless of the above settings.
MS1230-E-00
- 72 -
2010/9