AK8858 Datasheet, PDF (25/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[AK8858]
Additionary, the AK8858 can change the position, width and current value of clamp pulse via register Clamp
Control 1 Register (R/W) [Sub Address 0x01] and Clamp Control 2 Register (R/W) [Sub Address 0x02].
Sub Address: 0x01
bit 7
bit 6
CLP-
WIDTH1
CLP-
WIDTH0
Default Value
0
0
bit 5
CLP-
STAT1
0
bit 4
CLP-
STAT0
0
bit 3
Reserved
0
bit 2
BCLP-
STAT2
0
Default Value: 0x00
bit 1
bit 0
BCLP-
STAT1
BCLP-
STAT0
0
0
Sub Address: 0x02
bit 7
bit 6
Reserved
Reserved
Default Value
0
0
bit 5
Reserved
0
bit 4
YPBPRCP
0
bit 3
UDG1
0
bit 2
UDG0
0
Default Value: 0x01
bit 1
bit 0
CLPG1 CLPG0
0
1
BCLPSTAT[2:0]-bit: Set the position of analog backporch clamp pulse.
Setting
000
Clamp position
Same position with “CLPSTAT” setting
001
(1/128)H delay from “CLPSTAT” setting
010
(2/128)H delay from “CLPSTAT” setting
011
(3/128)H delay from “CLPSTAT” setting
100
(4/128)H advance from “CLPSTAT” setting
101
(3/128)H advance from “CLPSTAT” setting
110
(2/128)H advance from “CLPSTAT” setting
111
(1/128)H advance from “CLPSTAT” setting
Set only the position of analog backporch clamp pulse.
CLPSTAT[1:0]-bit: Set the position of clamp pulse.
Setting
Clamp position
00
Sync tip/ middle/ bottom clamp: Center of horizontal sync
Backporch clamp: Center of backporch interval
01
(1/128)H delay
10
(2/128)H advance
11
(1/128)H advance
The positions of all clamp pulse are changed.
Notes
Notes
CLPWIDTH[1:0]-bit: Set the clamp pulse width. Pulse width is change according to sampling clock units.
Setting
Clamp width
Notes
00
7 clock
01
15 clock
Clock units
525i, 625i: 27MHz
10
31 clock
525p, 625p: 54MHz
11
63 clock
The width of all clamp pulse is changed.
YPBPRCP-bit: Set the clamp position of PbPr signal of YPbPR component video signal.
Setting
Clamp position
0
Sync tip timing
1
Backporch timing
Notes
MS1230-E-00
- 25 -
2010/9