AK8858 Datasheet, PDF (34/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[7.12] VBI period decode data
The AK8858 decode data during VBI period can be selected via register.
[AK8858]
Settings for decode data in the VBI period
Name
Setting
value
Decode data
[00]
Black level output
VBIDEC0 _[01]
~
VBIDEC1 _[10]
Monochrome mode
Sliced data output
Sub Address: 0x05 [7:6]
Notes
Y = 0x10
Cb/Cr = 0x80
Y = data converted to 601 level
Cb/Cr = 0x80
Y/Cb/Cr = value corresponding to slice level
(Value set at Hi/Low Slice Data Set Register)
[11]
Reserved
Reserved
Note: (525i) Lne1~Line9 and Line263.5~Line272.5
(625i) Line623.5~Line6.5 and Line311~Line388
(525p) Line1~Line18
(625p) Line621~Line10
During the above period, these values are unaffected by the VBIDEC[1:0]-bits setting.
The output code during this period is black level code (Y=0x10, Cb/Cr=0x80).
[7.13] VLOCK mechanism
The AK8858 synchronizes internal operation with the input signal frame structure. If, for example, the frame
structure of the input signal comprises 524 lines, the internal operation will have structure of 524 lines per frame.
This mechanism is termed the VLOCK mechanism. If an input signal changes from a structure of 525 lines per
frame to one of 524 lines per frame, internal operation will change accordingly, and the VLOCK mechanism will
go to UnLock via a pull-in process. In such case, the UnLock status can be confirmed via the control register
[VLOCK-bit*]. Note that the time required for locking of the VLOCK mechanism upon channel or other input
signal switching will be about 4 frames (*Sub-address:0x22-“bit1”)
Furthermore, the AK8858 synchronizes internal operation with the vertical SYNC of the input signal. This
mechanism is termed the direct LOCK mechanism.
Setting for Vertical SYNC mechanism
Name
Definition
VERTS
Vertical SYNC mechanism
[0]: VLOCK mechanism
[1]: Direct LOCK mechanism
Sub Address: 0x03 [7]
MS1230-E-00
- 34 -
2010/9