AK8858 Datasheet, PDF (66/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[9.1.2] Clamp Control 1 Register (R/W) [Sub Address 0x01]
Clamp pulse setting.
[AK8858]
Sub Address: 0x01
bit 7
bit 6
CLP-
WIDTH1
CLP-
WIDTH0
Default Value
0
0
bit 5
CLP-
STAT1
0
bit 4
CLP-
STAT0
0
bit 3
Reserved
0
bit 2
BCLP-
STAT2
0
Default Value: 0x00
bit 1
bit 0
BCLP-
STAT1
BCLP-
STAT0
0
0
Clamp Control 1 Register
BIT Register Name
R/W Definition
Backporch clamp start position setting.
The default position is at the center of Sync signal.
[ BCLPSTAT2 : BCLPSTAT0 ]
bit 0 BCLPSTAT0
~~
bit 2 BCLPSTAT2
Back Porch
Clamp Start
[000]: Same position as default “CLPSTAT”
[001]: (1/128)H delay from “CLPSTAT”
R/W [010]: (2/128)H delay from “CLPSTAT”
[011]: (3/128)H delay from “CLPSTAT”
[100]: (4/128)H advance from “CLPSTAT”
[101]: (3/128)H advance from “CLPSTAT”
[110]: (2/128)H advance from “CLPSTAT”
[111]: (1/128)H advance from “CLPSTAT”
bit 3 Reserved
Reserved
R/W Reserved
Clamp pulse start position setting.
The default position is at the center of horizontal Sync signal.
bit 4 CLPSTAT0
[ CLPSTAT1 : CLPSTAT0 ]
~~
Clamp Start R/W [00]: Center of horizontal sync (default position)
bit 5 CLPSTAT1
[01]: (1/128)H delay
[10]: (2/128)H advance
[11]: (1/128)H advance
Clamp pulse width setting.
Pulse width is change according to sampling clock units.
bit 6 CLPWIDTH0
~~
bit 7 CLPWIDTH1
Clamp Pulse
Width
[ CLPWIDTH1 : CLPWIDTH0 ]
R/W [00]: 7-clk
[01]: 15-clk
[10]: 31-clk
[11]: 63-clk
MS1230-E-00
- 66 -
2010/9