AK8858 Datasheet, PDF (28/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[AK8858]
SETUP-bit: Setting for presence or absence of input signal SETUP.
Setting ON/OFF
Notes
0
Setup absent
With the Setup present setting,
the luminance and color signals are processed as follows:
Yout = (YIN-7.5IRE)/0.925
Uout = UIN/0.925, Vout = VIN/0.925
1
Setup present
YOUT: Y after setup
YIN: Y before setup
UOUT: U after setup
UIN: U before setup
VOUT: V after setup
VIN: V before setup
In auto detection mode, the default setting of Setup processing via register STUPATOFF-bit of Control 2
Register (R/W) [Sub Address 0x0D]-bit6 is shows as follows.
Detected signal
Register setting
Setup-bit
STUPATOFF-bit
NTSC-M,J
PAL-B,D,G,H,I,N
0
0
1
PAL-Nc , 60
SECAM
1
0
1
PAL-M
NTSC-4.43
0
0
1
1
0
1
In case of YPbPr signal input, auto Setup processing is not performed.
Setup present/ absent
Setup absent
Setup absent
Setup present
Setup present
Setup present
Setup absent
Setup present
Setup present
AUTODET-bit: Settings for auto detection of input signal (auto detetction mode)
Setting
ON/OFF
Notes
0
OFF
Manual setting
1
ON
CSSL-bit: Settings for sync and video signal ratio of input signal.
Setting
0
1
S/V ratio
300/700
286/714
Only available when component input signal is selected.
Notes
EIA-770.2
EIA-770.1
CSCL-bit: Settings for color level of component input signal.
Setting
Video level
0
700mV
1
714mV
Only available when component input signal is selected.
Notes
EIA-770.2
EIA-770.1
CMPSEL-bit: Interlace and Progressive setting for YPbPr component input signal.
Setting
YPbPr component video signal
0
Interlace (525i/ 625i)
1
Progressive (525P/ 625P)
VERTS-bit: Select of VLOCK or Direct Lock
Setting
SYNC mechanism
0
VLOCK mechanism
1
Direct LOCK mechanism
Notes
MS1230-E-00
- 28 -
2010/9