AK8858 Datasheet, PDF (40/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[7.21] Clock generation
The AK8858 operates in the following three clock modes:
1. Line-locked clock mode.
2. Frame-locked clock mode
3. Fixed clock mode
The clock mode can be set via register.
[AK8858]
[7.21.1] Line-locked clock mode
The “line-locked clock” is generated by PLL using horizontal sync signal within the input signal. If no input
signal is present, the AK8858 will switch from this mode to fixed-clock mode.
[7.21.2] Frame-locked mode
The “frame-locked clock” is generated by PLL using vertical sync signal within the input signal. If no signal is
present, the AK8858 will switch from this mode to fixed-clock mode.
[7.21.3] Fixed-clock mode
No PLL control is applied in this mode, which is enabled only when either it is set via the register or no input
signal is present. The sampling clock in this mode is 27MHz or 54MHz. In this mode, data capture cannot be
performed in EAV (end of active video), and must be performed in SAV (start of active video) format. The
number of pixels per line is not guarantee in this mode, but data guarantee is performed in the interval from
SAV to EAV.
In the line-locked and frame-locked clock modes, the clock is synchronized with the input signal and the output
is ITU-R BT.656 compliant. It should be noted that ITU-R BT.656 compliant output may not be possible with
low-quality input signals.
It should be noted that in the fixed-clock mode the sample number will be insufficient for ITU-R BT.656
compliance, due to non-synchronization of the input data.
[7.21.4] Auto transition mode
The AK8858 transition function automatically switches among the above modes and selects the optimum one,
and when no input signal is present, it switches to the fixed-clock mode.
Settings for selection of clock generation mode.
CLKMODE[1:0]-bit
Clock generation mode
00
Automatic
01
Line-locked
10
Frame-locked
11
Fixed-clock
Sub Address 0x0C [7:6]
Notes
MS1230-E-00
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2010/9