AK8858 Datasheet, PDF (65/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[9.1] Register setting overview
[AK8858]
[9.1.1] Input Channel Select Register (R/W) [Sub Address 0x00]
Input signal channel selection and clock mode selection register.
Sub Address: 0x00
bit 7
bit 6
CLKMOD SELSRC1
Default Value
0
0
bit 5
SELSRC0
0
bit 4
ADC3SEL
0
bit 3
ADC2SEL
0
bit 2
ADC1SEL2
0
Default Value: 0x00
bit 1
bit 0
ADC1SEL1 ADC1SEL0
0
0
Input Channel Select Register
BIT Register Name
bit 0 ADC1SEL0
~
~
bit 2 ADC1SEL2
ADC 1 Select
bit 3 ADC2SEL
bit 4 ADC3SEL
bit 5 SELSRC0
~
~
bit 6 SELSRC1
bit 7 CLKMOD
ADC 2 Select
ADC 3 Select
Select Source
Clock Mode
R/W Definition
ADC1 input signal selection
000: AIN1
001: AIN2
R/W 010: AIN3
011: AIN4
100: AIN5
101: AIN6
Virtual ADC2 input signal selection
R/W 0: AIN7
1: AIN8
Virtual ADC3 input signal selection
R/W 0: AIN9
1: AIN10
Decode signal selection
00: Composite (CVBS)
R/C 01: S-Video
10: Component (YPbPr)
11: No input signal (Analog block is powerdown)
Clock mode selection
R/W 0: For crystal
1: External clock input (clock generator etc.)
MS1230-E-00
- 65 -
2010/9