AK8858 Datasheet, PDF (35/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[AK8858]
[7.14] Adjustment of Y and C timing
Adjustment of the position between Y and C signal
Sub Address: 0x08 [2:0]
YCDELAY[2:0]-bit
001
Y and C timing
Y advance 1 sample toward Cb, Cr.
Notes
010
Y advance 2 sample toward Cb, Cr.
011
Y advance 3 sample toward Cb, Cr.
000
No delay and advance.
Default
101
Y delay 3 sample toward Cb, Cr.
110
Y delay 2 sample toward Cb, Cr.
111
Y delay 1 sample toward Cb, Cr.
100
Reserved
Note: 1sample of Interlace output is about 74ns / 1 sample of progressive output is about 37ns.
Relation between Y and C timing regardless the above setting is shown as follows.
YCDELAY[2:0] = [000] ^{Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3 Cb2 Y4 Cr2 Y5}
Y/C default
YCDELAY[2:0] = [111] ^{Cb0 Y857 Cr0 Y0 Cb1 Y1 Cr1 Y2 Cb2 Y3 Cr2 Y4} _{1sample delay}
YCDELAY[2:0] = [001] ^{Cb0 Y1 Cr0 Y2 Cb1 Y3 Cr1 Y4 Cb2 Y5 Cr2 Y6} 1sample adv.
[7.15] Adjustment of active video start position
Adjustment of the active video start position
ACTSTA[2:0]-bit
001
010
011
000
101
110
111
100
Line and active video start
525 Line
124th sample
625 Line
134th sample
525 Line
125th sample
625 Line
135th sample
525 Line
126th sample
625 Line
136th sample
525 Line
123th sample
625 Line
133th sample
525 Line
120th sample
625 Line
130th sample
525 Line
121th sample
625 Line
131th sample
525 Line
122th sample
625 Line
132th sample
Reserved
Reserved
DTCLK
Notes
Sub Address: 0x08 [6:4]
D1 decode: 74ns delay
D2 decode: 37ns delay
D1 decode: 148ns delay
D2 decode: 74ns delay
D1 decode: 222ns delay
D2 decode: 111ns delay
Default（Normal position）
D1 decode: 222ns advance
D2 decode: 111ns advance
D1 decode: 148ns advance
D2 decode: 74ns advance
D1 decode: 74ns advance
D2 decode: 37ns advance
MS1230-E-00
- 35 -
2010/9