AK8858 Datasheet, PDF (48/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[AK8858]
[7.26.2] Interface used timing signal
For connection with devices having no ITU-R BT.656 interface, the AK8858 DVALID signal output identifies the
active video interval by remaining low throughout that period, as shown in the following figure.
In RGB output mode, it is suggest to use this interface when output the valid data
[7.26.2.1] HD pin output
AK8858 output HD signal for horizontal synchronization.
Pin name
HD
Interlace /
Progressive
Interlace
Progressive
525-Line
Low for 4.7us at
15.734 kHz interval.
Low for 2.35us at
31.468 kHz interval.
625-Line
Low for 4.7us at
15.625 kHz interval.
Low for 2.35us at
31.250 kHz interval.
[7.26.2.2] VD_FLD or DVAL_FLD pin output
AK8858 output VD, FIELD and DVALID signal.
Pin name
VD_FLD
DVAL_FLD
Interlace /
Progressive
Interlace
Progressive
Interlace
Progressive
Output
VD
FIELD
VD
FIELD
DVALID
FIELD
DVALID
FIELD
525-Line
625-Line
Low output at Line4~Line6 or
Line266.5~Line269.5
Low output at Line1~Line3.5 or
Line313.5~Line315
ODD-Field: Low, EVEN-Field: High
Low output at Line7~Line12
Low output at Line1~Line5
Toggle by each flame
Low during active video interval
ODD-Field: Low, EVEN-Field: High
Low during active video interval
Toggle by each flame
Select output from VD_FLD pin
Name
VDFSEL
Select output from DVAL_FLD pin
Name
DVALFSEL
Definition
[0]: VD
[1]: FIELD
Definition
[0]: DVALID
[1]: FIELD
Sub Address: 0x07 [5]
Notes
Sub Address: 0x07 [6]
Notes
MS1230-E-00
- 48 -
2010/9