AK8858 Datasheet, PDF (23/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[AK8858]
[7.2] Analog Interface
The AK8858 accepts composite video signal (CVBS), S(Y/C) video signal, YPbPr component video signal
(D1/D2) input with 10 input pins available for this purpose.
Sub Address:0x00
bit 7
bit 6
CLKMOD SELSRC1
Default Value
0
0
bit 5
SELSRC0
0
bit 4
ADC3SEL
0
bit 3
ADC2SEL
0
bit 2
ADC1SEL2
0
Default Value:0x00
bit 1
bit 0
ADC1SEL1 ADC1SEL0
0
0
The connection settings are shown below.
ADC1SEL[2:0]-bit: Input selection for ADC1. (for CVBS or Y)
Setting
ADC1 Input
000
AIN1
001
AIN2
010
AIN3
011
AIN4
100
AIN5
101
AIN6
ADC2SEL-bit: Input selection for ADC2 (VADC2). (for C or Pb)
Setting
ADC2 Input
0
AIN7
1
AIN8
ADC3SEL-bit: Input selection for ADC3 (VADC2). (for Pr)
Setting
ADC3 Input
0
AIN9
1
AIN10
SELSRC[1:0]-bit: Decode signal type setting bit.
Setting
Input signal
00
Composite (CVBS) video signal
01
S-Video signal
10
Component video signal
11
Analog power-down (CLAMP, AAF, PGA, ADC is power-down)
[7.3] Input Clock mode
CLKMOD-bit: Input clock setting bit.
Setting
Input clock
0
For crystal
1
External clock input (clock generator)
MS1230-E-00
- 23 -
2010/9