AK8858 Datasheet, PDF (24/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[AK8858]
[7.4] Analog clamp circuit
The analog circuit of the AK8858 clamps the input signal to the reference level. The way to clamp the input
signal is as follows.
The clamp timing pulse, with its origin at the falling edge of the internally synchronized and separated sync
signal, is generated at approximately the central position of the sync signal.
Input signal
Composite (CVBS)
video signal
S(Y/C) video
signal
Component video
signal
Y signal
C signal
Y signal
Pb signal
Pr signal
Clamp Level
Sync tip level
Sync tip level
Pedestal level
Sync tip level
Pedestal level
Pedestal level
Clamp pulse position
Sync tip
Sync tip
Sync tip of Y
Sync tip
Clamp timing is performs by sync tip clamp or
backporch clamp.
If Pb and Pr signal have sync signl, set clamp timing to
backporch clamp.
Clamp Timing Pulse
CVBS
Analog sync tip clamp
Y
Analog sync tip clamp
C
Analog middle clamp
Y
Analog sync tip clamp
Pb
Analog middle clamp
Pr
Analog middle clamp
Y
Analog sync tip clamp
Pb
Analog backporch clamp
Pr
Analog backporch clamp
MS1230-E-00
- 24 -
2010/9