AK8858 Datasheet, PDF (36/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

With the default value, the start position is as follows (with ITU-R BT.601 format compliance).
[AK8858]
OH
122sample(525Line)
Active video start
OH
132sample(625Line)
Active video start
[7.16] PGA
The AK8858 analog PGA and digital PGA are built internally.
The analog PGA value can be set in range of -3dB to 6dB, and the gain step is 3dB/step.
The digital PGA value can be set in range -0.25dB to 4dB, and the gain step is not log scale.
Digital PGA gain equation:
Gain(dB) = 20LOG_⎜⎛ ^{(5× PGA)+ 497} _⎟⎞
⎝ ⁵¹² ⎠
*PGA: PGA1 or PGA2 register value (Decimal)
Default gain setting is 0x54(HEX)=1.3dB. (Analog:0dB + Digital:1.3dB)
At the default setting, when the composite video signal input with 0.5Vpp is input to the AIN pin, the decode
gain setting is set to appropriate range.
PGA1 is used for CVBS and Y signals gain processing.
Setting for PGA1 value
Name
Definition
DPGA1_0
~
DPGA1_5
APGA1_0
~
APGA1_1
Digital PGA1 gain setting.
PGA gain is set by above equation.
Analog PGA1 gain setting.
[00]: −3dB
[01]: 0dB
[10]: +3dB
[11]: +6dB
Sub Address: 0x0E [7:0]
PGA2 is used for C, Pb, and Pr signals gain processing.
Setting for PGA2 value
Name
Definition
DPGA2_0
~
DPGA2_5
APGA2_0
~
APGA2_1
Digital PGA2 gain setting.
PGA gain is set by above equation.
Analog PGA2 gain setting.
[00]: −3dB
[01]: 0dB
[10]: +3dB
[11]: +6dB
Sub Address: 0x0F [7:0]
This register also can be used to read the current setting of the AGC setting.
If AGC is enable, the Gain1/2 Control Register[7:0]-bit setting value has no effect.
If AGC is disable, the Gain1/2 Control Register setting can be manually entered.
MS1230-E-00
- 36 -
2010/9