AK8858 Datasheet, PDF (4/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[AK8858]
[7.29.7] Sepia output .................................................................................................................................................... 57
[7.29.8] U/ V Filter ......................................................................................................................................................... 58
[7.30] VBI information decoding ..................................................................................................................................... 59
[7.31] Internal status indicators Register....................................................................................................................... 60
[7.31.1] No signal detect .............................................................................................................................................. 60
[7.31.2] VLOCK status.................................................................................................................................................. 60
[7.31.3] Interlace Status ............................................................................................................................................... 60
[7.31.4] Status of color killer operation ...................................................................................................................... 60
[7.31.5] Status of clock mode ...................................................................................................................................... 60
[7.31.6] Luminance over flow ...................................................................................................................................... 60
[7.31.7] Chrominance over flow .................................................................................................................................. 61
[7.31.8] Field status ...................................................................................................................................................... 61
[7.31.9] AGC status ...................................................................................................................................................... 61
[7.32] Macrovision signal detection ............................................................................................................................... 61
[7.32.1] Macrovision Color Stripe Cancel................................................................................................................... 61
[7.33] Auto detection result of input video signal ......................................................................................................... 62
[8] Device control interface ................................................................................................................................................ 63
[8.1] I2C bus SLAVE Address ......................................................................................................................................... 63
[8.2] I2C control sequence .............................................................................................................................................. 63
[8.2.1] Write sequence ................................................................................................................................................. 63
[8.2.2] Read sequence.................................................................................................................................................. 63
[9] Register Definitions ....................................................................................................................................................... 64
[9.1] Register setting overview ....................................................................................................................................... 65
[9.1.1] Input Channel Select Register (R/W) [Sub Address 0x00]............................................................................. 65
[9.1.2] Clamp Control 1 Register (R/W) [Sub Address 0x01] .................................................................................... 66
[9.1.3] Clamp Control 2 Register (R/W) [Sub Address 0x02] .................................................................................... 67
[9.1.4] Miscellaneous Setting Register (R/W) [Sub Address 0x03] .......................................................................... 68
[9.1.5] Input Video Standard Register (R/W) [Sub Address 0x04] ............................................................................ 69
[9.1.6] Output Format Register (R/W) [Sub Address 0x05] ....................................................................................... 70
[9.1.7] NDMODE Register (R/W) [Sub Address 0x06] ................................................................................................ 71
[9.1.8] Output Control Register (R/W) [Sub Address 0x07] ...................................................................................... 72
[9.1.9] Output Data Start and Delay Control Register (R/W) [Sub Address 0x08]................................................... 73
[9.1.10] Output Data Format Register (R/W) [Sub Address 0x09] ............................................................................ 74
[9.1.11] AGC & ACC Control Register (R/W) [Sub Address 0x0A] ........................................................................... 75
[9.1.12] Control 0 Register (R/W) [Sub Address 0x0B].............................................................................................. 76
[9.1.13] Control 1 Register (R/W) [Sub Address 0x0C].............................................................................................. 77
[9.1.14] Control 2 Register (R/W) [Sub Address 0x0D].............................................................................................. 78
[9.1.15] PGA1 Control Register (R/W) [Sub Address 0x0E] ...................................................................................... 79
[9.1.16]PGA2 Control Register (R/W) [Sub Address 0x0F] ....................................................................................... 79
MS1230-E-00
-4-
2010/9