AK8858 Datasheet, PDF (77/96 Pages) Asahi Kasei Microsystems – PS/SD Multi Format Video Decoder

[9.1.13] Control 1 Register (R/W) [Sub Address 0x0C]
[AK8858]
Sub Address: 0x0C
bit 7
bit 6
CLKMODE1 CLKMODE0
Default Value
0
0
bit 5
INTPOL1
0
bit 4
INTPOL0
0
bit 3
UVFILSEL1
0
bit 2
UVFILSEL0
0
Default Value: 0x00
bit 1
bit 0
YCSEP1 YCSEP0
0
0
Control 1 Register
BIT Register Name
bit 0 YCSEP0
~
~
bit 1 YCSEP1
YC Separation
Control
bit 2 UVFILSEL0
~
~
bit 3 UVFILSEL1
UV Filter Select
bit 4 INTPOL0
~
~
bit 5 INTPOL1
bit 6 CLKMODE0
~
~
bit 7 CLKMODE1
Interpolator Mode
Select
Clock Mode Select
R/W Definition
Y/C separation setting YCSEP[1:0]
00: Adaptive Y/C separation
R/W 01: 1-dimensional Y/C separation
10: 2-dimensional Y/C separation
11: Reserved
UV filter setting
(CVBS or S-video input)
UVFILSEL0
0: Wide 1
1 Narrow 1
R/W
(YPbPr input)
00: Middle 1
01: Middle 2
10: Wide 2
11: Narrow 2
Pixel interpolator setting
INTPOL[1:0]
R/W
00: Auto
01: ON
10: OFF
11: Reserved
Clock mode setting
CLKMODE[1:0]
R/W
00: Automatic transition mode
01: Line-locked clock mode
10: Frame-locked clock mode
11: Fixed-clock mode
MS1230-E-00
- 77 -
2010/9