AK4648 Datasheet, PDF (85/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
■ Register Definitions
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Power Management 1 PMSPR PMVCM PMMIN PMSPL PMLO PMDAC
0
PMADL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RD
R/W
Default
0
0
0
0
0
0
0
0
PMADL: MIC-Amp Lch and ADC Lch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMDAC: DAC Power Management
0: Power down (default)
1: Power up
PMLO: Stereo Line Out Power Management
0: Power down (default)
1: Power up
PMSPL: Speaker-Amp Lch Power Management
0: Power down (default)
1: Power up
PMMIN: MIN Input Power Management
0: Power down (default)
1: Power up
PMMIN or PMAINL3 bit should be set to “1” for playback.
PMVCM: VCOM Power Management
0: Power down (default)
1: Power up
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits of 00H, 01H, 02H, 10H, 20H and MCKO bits are “0”.
PMSPR: Speaker-Amp Rch Power Management
0: Power down (default)
1: Power up
Each block can be powered-down respectively by writing “0” to each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0” in the 00H, 01H, 02H, 10H and 20H addresses and MCKO bit is “0”, all
blocks are powered-down. The register values remain unchanged.
When neither ADC nor DAC are powered-up, external clocks may not be present. When ADC or DAC is powered-up,
external clocks must always be present.
MS0625-E-01
- 85 -
2007/06