AK4648 Datasheet, PDF (110/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
(11) Power Up of DAC, MIN-Amp and Speaker-Amp:
a. Mono SPK Mode (When Lch Speaker-Amp, SPLP/SPLN pins are used.): PMDAC = PMMIN = PMSPL
bits = “0” → “1”
b. Stereo SPK Mode or High Power Mono SPK Mode: PMDAC = PMMIN = PMSPL = PMSPR bits = “0”
→ “1”
The DAC enters an initialization cycle when the PMDAC bit is changed from “0” to “1” at PMADL and
PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2's complement, “0”. The DAC
output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is
“1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by
IVL/R7-0 bits) during an initialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC
operation starts from the gain set by IVL/R7-0 bits.
(12) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
The powered-down channel is Hi-Z in Mono SPK Mode.
(13) Enter the power-save-mode of Speaker-Amp : SPPSN bit = “1” → “0”
(14) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “1” Æ “0”
(15) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMMIN = PMSPL = PMSPR bits = “1” → “0”
MS0625-E-01
- 110 -
2007/06