AK4648 Datasheet, PDF (78/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
<Speaker-Amp Control Sequence>
Lch Speaker-Amp is powered-up/down by PMSPL bit and Rch Speaker-Amp is powered-up/down by PMSPR bit.
Power-save mode of both Lch and Rch Speaker-Amps are controlled by SPPSN bit.
When PMSPL (PMSPR) bit is “0”, both SPLP (SPRP) and SPLN (SPRN) pin are in Hi-Z state. When PMSPL (PMSPR)
bit is “1” and SPPSN bit is “0”, the Speaker-Amp enters power-save mode. In this mode, SPLP (SPRP) pin is placed in
Hi-Z state and SPLN (SPRN) pin goes to HVDD/2 voltage. Power-save mode can reduce the pop noise at power-up and
power-down.
When The PDN pin is changed from “L” to “H” after power-up and PMSPL (PMSPR) bit is set to “1”, SPLP (SPRP) and
SPLN (SPRN) pins are in power-save mode. When changing the output mode of Speaker-Amp, PMSPL and PMSPR bits
should be set to “0”.
PMSPL bit
PMSPR bit
0
1
SPPSN bit
Mode
SPLP pin
SPRP pin
SPLN pin
SPRN pin
x
Power-down
Hi-Z
Hi-Z
0
Power-Save
Hi-Z
HVDD/2
1
Normal Operation Normal Operation Normal Operation
Table 68. Setting of Speaker-Amp Mode (x: Don’t care)
(default)
PMSPL bit
PMSPR bit
SPPSN bit
SPLP pin,
SPRP pin
Hi-Z
Hi-Z
SPLN pin,
HVDD/2
SPRN pin ^Hi-Z
HVDD/2
Hi-Z
Figure 57. Power-up/Power-down Timing for Speaker-Amp
MS0625-E-01
- 78 -
2007/06