AK4648 Datasheet, PDF (101/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
Analog Supply ^10u
2.6 ∼ 3.6V
10
Analog
Digital
Ground
Ground
Line In
2.2u
0.1u ^0.1u
TEST VCOM AVDD LIN1 MPWR CAD0 NC
Line out
220
1u
220
1u
LIN4 RIN2 LIN3 VSS1 RIN3 SCL SDTI
ROUT LOUT LIN2
NC
NC
RIN1 LRCK
SPRP SPRN RIN4
NC
NC
SDA BICK
Analog Supply ^10u
2.6 ∼ 5.0V
VSS2
HPL DVDD SDTO MCKO
HVDD SPLP HVCM HPR PDN TVDD TVDD
Mono Speaker
NC SPLN VSS2 MUTET VSS3 MCKI NC
0.1u
0.1u
Top View
Headphone
(See Figure 51 and Figure 53)
μP
CPU
Digital
1.6 ∼ 3.6V
Notes:
- VSS1, VSS2, and VSS3 of the AK4648 should be distributed separately from the ground of external
controllers.
- All digital input pins should not be left floating.
- When AIN3 bit = “1”, PLL is not available.
- When the AK4648 is used in master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4648.
- When DVDD is supplied from AVDD via 10Ω resistor, a capacitor should be 0.1μF or less.
Figure 70. Typical Connection Diagram
(AIN3 bit = “1”: PLL is not available, CAD0 = “0”, Line Input, High Power Mono SPK Mode)
MS0625-E-01
- 101 -
2007/06