AK4648 Datasheet, PDF (112/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
■ Headphone-amp Output
FS3-0 bits _0,000
(Addr:05H, D5&D2-0)
(1)
HPG3-0 bits
(Addr:0FH, D7-4)
1011
(2)
DACH bit
(Addr:0FH, D0)
FBEQ bit
(Addr: 0EH, D2)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMMIN bit
(Addr:00H, D5)
0
E1H
(3)
(4)
18H
(5)
(6)
1,111
1010
1
91H
28H
(13)
E xa m p le :
P LL M aster M o d e
S a m p lin g F re q u e n c y: 4 4 .1 kH z
D V O L C b it = “1 ”(d e fa u lt)
D ig ita l V o lu m e L e v e l: − 8 d B , H P V o lu m e L e v e l: -3 d B
E Q : E n a b le
D e-em phases response: O F F
S oft M ute T im e : 25 6/fs, P seu do C ap -less M o de
(1 ) A dd r:0 5 H , D a ta :2 7H
0
(12)
(2 ) A dd r:0 F H , D a ta A 9 H
(3 ) A dd r:0 E H , D a ta 1 5H
(4 ) A dd r:0 9 H & 0 C H , D a ta 9 1 H
(5 ) A dd r:0 A H & 0 D H , D a ta 2 8 H
(6 ) A dd r:0 0 H , D a ta 6 4H
(11)
(7 ) A dd r:0 1 H , D a ta 3 D H
(8 ) A dd r:0 1 H , D a ta 7 9H
P la y b a c k
PMHPL/R/C bits
(Addr:01H, D5-4&D2)
HPMTN bit
(Addr:01H, D6)
HPL/R pins,
HVCM pin
(7)
(10)
(8)
(9)
(9 ) A dd r:0 1 H , D a ta 3 9H
(1 0 ) A d d r:0 1 H , D a ta 0 9 H
(1 1 ) A d d r:0 0 H , D a ta 4 0 H
Normal Output
(1 2 ) A d d r:0 E H , D a ta 1 1 H
(1 3 ) A d d r:0 F H , D a ta A 8 H
Figure 79. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4648 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC Æ HP-Amp”: DACH bit = “0” → “1”
Set up analog volume for HP-Amp (Addr: 0F, HPG3-0 bits)
(3) Enable 5-band Equalizer. (Boost amount is selected by Addr=25H-27H.): FBEQ bit = “0” Æ “1”
(4) Set up input volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(5) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the
initialization cycle, the DAC input digital data of both channels are internally forced to a 2's complement, “0”.
The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or
PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable
(ALC gain is set by IVL/R7-0 bits) during an initialization cycle (1059/fs=24ms@fs=44.1kHz). After the
initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.
(7) Power up headphone-amp:
a. Pseudo Cap-less Mode: PMHPL = PMHPR = PMHPC bits = “0” → “1”
b. Single-ended Mode: PMHPL=PMHPR bits = “0” Æ “1”
Output voltages of headphone-amp are still VSS2.
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1”
The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0μF±30%, the time constant (0.8 x HVDD/2) is τr = 120ms(typ.), 210ms(max.).
In Single-ended Mode, HVCM pin still outputs VSS2.
MS0625-E-01
- 112 -
2007/06