AK4648 Datasheet, PDF (109/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
■ Speaker-amp Output
FS3-0 bits _X,XXX
(Addr:05H, D5&D2-0)
1,111
(1)
(14)
DACS bit
(Addr:02H, D5)
(2)
SPKG2-0 bits
(Addr:03H, D4-3, D1)
ALC Control 1
(Addr:06H)
ALC Control 2
(Addr:08H)
000
XXH
XXH
(3)
(4)
(5)
001
3CH
C1H
ALC Control 3
(Addr:0BH)
ALC bit
(Addr:07H, D5)
XXH
0
(6)
(7)
00H
X
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
(8)
91H
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
18H
XXH
(9)
SPKMN bit
0
X
(Addr:21H, D6)
(10)
(15)
PMDAC bit
(Addr:00H, D2)
PMMIN bit
(Addr:00H, D5)
PMSPL/R bits
(Addr:00H, D7,D4)
SPPSN bit
(Addr:02H, D7)
SPLP pin
SPRP pin
SPLN pin
SPRN pin
(11)
(12)
(13)
Hi-Z
Normal Output Hi-Z
Hi-Z
HVDD/2 Normal Output HVDD/2 Hi-Z
Figure 77. Speaker-Amp Output Sequence
Example:
PLL Master Mode
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: 0dB
ALC: Enable, Stereo SPKMode
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:20H
(3) Addr:03H, Data:08H
(4) Addr:06H, Data:3CH
(5) Addr:08H, Data:E1H
(6) Addr:0BH, Data:00H
(7) Addr:07H, Data:20H
(8) Addr:09H & 0CH, Data:91H
(9) Addr:0AH & 0DH, Data:28H
(10) Addr:21H, Data:40H
(11) Addr:00H, Data:F4H
(12) Addr:02H, Data:A0H
Playback
(13) Addr:02H, Data:20H
(14) Addr:02H, Data:00H
(15) Addr:00H, Data:40H
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4648 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC Æ SPK-Amp”: DACS bit = “0” Æ “1”
(3) SPK-Amp gain setting: SPKG2-0 bits = “000” Æ “001”
(4) Set up Timer Select for ALC (Addr: 06H)
(5) Set up REF value for ALC (Addr: 08H)
(6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
When PMADL or PMADR bit is “1”, ALC for DAC path is disabled.
(8) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(9) Set up the output digital volume (Addr: 0AH and 0DH).
When DVOLC bit is “1” (default), DVL7-0 bits (Addr=0AH) set the volume of both channels. After DAC is
powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft
transition.
(10) Set up Speaker Output Mode: SPKMN bit: “0” Æ “1” (Stereo SPK Mode)
SPKMN bit should be set to “0” in Mono SPK Mode or High Power Mono SPK Mode.
MS0625-E-01
- 109 -
2007/06