AK4648 Datasheet, PDF (24/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
Parameter
Control Interface Timing (I²C Bus):
Symbol
min
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 50)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive Load on Bus
Cb
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Power-down & Reset Timing
PDN Pulse Width (Note 51)
tPD
150
PMADL or PMADR “↑” to SDTO valid (Note 52)
tPDV
-
Note 49. I²C is a registered trademark of Philips Semiconductors.
Note 50. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 51. AK4648 can be reset by the PDN pin = “L”.
Note 52. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1059
max Units
400
kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
-
μs
400
pF
50
ns
-
ns
-
1/fs
MS0625-E-01
- 24 -
2007/06