AK4648 Datasheet, PDF (25/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
■ Timing Diagram
MCKI
LRCK
1/fCLK
tCLKH
tCLKL
1/fs
tLRCKH
tLRCKL
tBCK
VIH
VIL
50%TVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
BICK
tBCKH
tBCKL
1/fMCK
50%TVDD
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
MCKO
50%TVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Note 53. MCKO is not available at EXT Master mode.
Figure 4. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK
tDBF
50%TVDD
BICK
(BCKP = "0")
50%TVDD
BICK
(BCKP = "1")
SDTO
SDTI
tBSD
tSDS
MSB
tSDH
50%TVDD
50%TVDD
VIH
VIL
Figure 5. Audio Interface Timing (PLL/EXT Master mode, DSP mode, MSBS bit = “0”)
MS0625-E-01
- 25 -
2007/06