AK4648 Datasheet, PDF (64/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
SPKG2-0 bits
MIN Æ SPLP/SPLN or SPRP/SPRN
ALC bit = “0”
ALC bit = “1”
000
+4.43dB
+6.43dB
(default)
001
+6.43dB
+8.43dB
010
+10.65dB
+12.65dB
011
+12.65dB
+14.65dB
100
0dB
+2dB
101
-6dB
-4dB
110
N/A
N/A
111
N/A
N/A
Table 53. MIN Input Æ Speaker-Amp Output Gain (typ.) at R_i = 20kΩ; N/A: Not available
■ Stereo Line Output (LOUT/ROUT pins)
When the LODIF bit is set to “0”, the LOUT/ROUT pins become stereo line mode. When DACL bit is “1”, Lch/Rch
signal of DAC is output from the LOUT/ROUT pins which is single-ended. When DACL bit is “0”, output signal is
muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ (min.). When the PMLO=LOPS bits
= “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ.). When the
LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing
PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to VSS1 by 20kΩ after AC coupled as
Figure 45. Rise/Fall time is 300ms(max.) at C=1μF and AVDD=3.3V. When PMLO bit = “1” and LOPS bits = “0”, stereo
line output is in normal operation.
LOVL bit set the gain of stereo line output.
When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R)/2 mono signal.
When LOM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to
LOUT and ROUT pins as (L+R)/2 mono signal.
DAC
DACL bit
LOVL bit
LOUT pin
ROUT pin
LOPS
0
1
Figure 44. Stereo Line Output
PMLO
Mode
LOUT/ROUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 54. Stereo Line Output Mode Select
LOVL
Gain
Output Voltage (typ.)
0
0dB
0.6 x AVDD
(default)
1
+2dB
0.757 x AVDD
Table 55. Stereo Line Output Volume Setting
(default)
MS0625-E-01
- 64 -
2007/06