AK4648 Datasheet, PDF (100/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
SYSTEM DESIGN
Figure 69 and Figure 70 show the system connection diagram of the AK4648. The evaluation board [AKD4648]
demonstrates the optimum layout, power supply arrangements and measurement results.
Analog Supply ^10u
2.6 ∼ 3.6V
10
Analog
Digital
Ground
Ground
Internal MIC
External MIC
2.2u
0.1u 0.1u
Line In
Mono In
Line out
220
1u
220
1u
Analog Supply ^10u
2.6 ∼ 5.0V
Stereo Speaker
TEST VCOM AVDD LIN1 MPWR CAD0 NC
LIN4 RIN2 MIN VSS1 VCOC SCL SDTI
ROUT LOUT LIN2
NC
NC
RIN1 LRCK
SPRP SPRN RIN4
NC
NC
SDA BICK
VSS2
HPL DVDD SDTO MCKO
HVDD SPLP HVCM HPR PDN TVDD TVDD
NC SPLN VSS2 MUTET VSS3 MCKI NC
0.1u
0.1u
Top View
Headphone
(See Figure 51 and Figure 53)
μP
CPU
Digital
1.6 ∼ 3.6V
Notes:
- VSS1, VSS2, andVSS3 of the AK4648 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK4648 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC/RIN3 pin is not needed.
- When the AK4648 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC/RIN3 pin is should be
connected as shown in Table 5.
- When the AK4648 is used in master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4648.
- When DVDD is supplied from AVDD via 10Ω resistor, a capacitor should be 0.1μF or less.
Figure 69. Typical Connection Diagram (AIN3 bit = “0”, CAD0 = “0”, MIC Input, Stereo SPK Mode)
MS0625-E-01
- 100 -
2007/06