AK4648 Datasheet, PDF (67/119 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP/SPK-AMP

[AK4648]
■ Full-differential Mono Line Output (LOP/LON pins)
When LODIF bit = “1”, LOUT/ROUT pins become LOP/LON pins, respectively. Lch/Rch signal of DAC or
LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins which is full-differential as (L+R)/2 signal. The
load impedance is 10kΩ (min.) for LOP and LON pins, respectively. When the PMLO bit = “0”, the mono line output
enters power-down mode and the output is Hi-Z. When the PMLO bit is “1” and LOPS bit is “1”, mono line output enters
power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “0”. When PMLO
bit = “1” and LOPS bit = “0”, mono line output enters in normal operation. LOVL bit set the gain of mono line output.
When L4DIF=LODIF bits = “1”, full-differential output signal is as follows: (LOP) − (LON) = (IN4+) − (IN4−).
DAC
DACL bit _{LOVL bit}
LOP pin
LON pin
PMLO
0
1
Figure 48. Mono Line Output
LOPS
Mode
LOP
LON
x
Power-down
Hi-Z
Hi-Z
1
Power-save
Hi-Z
VCOM
0
Normal Operation Normal Operation Normal Operation
Table 56. Mono Line Output Mode Setting (x: Don’t care)
(default)
LOVL
0
1
Gain
Output Voltage (typ.)
+6dB
1.2 x AVDD
(default)
+8dB
1.5 x AVDD
Table 57. Mono Line Output Volume Setting
PMLO bit
LOPS bit
LOP pin
Hi-Z
Hi-Z
LON pin _Hi-Z ^VCOM
VCOM
Hi-Z
Figure 49. Power-up/Power-down Timing for Mono Line Output
MS0625-E-01
- 67 -
2007/06